[all-commits] [llvm/llvm-project] 8fa824: [ARM] Add predicated add reduction patterns

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8fa824d7a36d8570b857d5a13e83a532498557ed
      https://github.com/llvm/llvm-project/commit/8fa824d7a36d8570b857d5a13e83a532498557ed
  Author: David Green <david.green at arm.com>
  Date:   2020-07-22 (Wed, 22 Jul 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll

  Log Message:
  -----------
  [ARM] Add predicated add reduction patterns

Given a vecreduce.add(select(p, x, 0)), we can convert that to a
predicated vaddv, as the else value for the select is the identity
value, a zero. That is what this patch does for the vaddv, vaddva,
vaddlv and vaddlva instructions, copying the existing patterns to also
handle predication through a select.

Differential Revision: https://reviews.llvm.org/D84101