[all-commits] [llvm/llvm-project] 3a3419: [ARM] Fix Asm/Disasm of TBB/TBH instructions

[David Spickett via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3a3419460647612fba9dbecbd770fc8c84bbc05a
      https://github.com/llvm/llvm-project/commit/3a3419460647612fba9dbecbd770fc8c84bbc05a
  Author: David Spickett <david.spickett at linaro.org>
  Date:   2020-07-22 (Wed, 22 Jul 2020)

  Changed paths:
    M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    M llvm/test/MC/ARM/thumb2-diagnostics.s
    A llvm/test/MC/Disassembler/ARM/thumb2-diagnostic.txt

  Log Message:
  -----------
  [ARM] Fix Asm/Disasm of TBB/TBH instructions

Summary:
This fixes Bugzilla #46616 in which it was reported
that "tbb  [pc, r0]" was marked as SoftFail
(aka unpredictable) incorrectly.

Expected behaviour is:
* ARMv8 is required to use sp as rn or rm
  (tbb/tbh only have a Thumb encoding so using Arm mode
  is not an option)
* If rm is the pc then the instruction is always
  unpredictable

Some of this was implemented already and this fixes the
rest. Added tests cover the new and pre-existing handling.

Reviewers: ostannard

Reviewed By: ostannard

Subscribers: kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D84227