[all-commits] [llvm/llvm-project] f1ae96: [AArch64][GlobalISel] Fix TLS accesses clobbering ...

[AE via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f1ae96d9bfb807ded8019e851f2663ef18a4130c
      https://github.com/llvm/llvm-project/commit/f1ae96d9bfb807ded8019e851f2663ef18a4130c
  Author: Amara Emerson <amara at apple.com>
  Date:   2020-07-21 (Tue, 21 Jul 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll
    M llvm/test/CodeGen/AArch64/arm64-tls-darwin.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Fix TLS accesses clobbering registers incorrectly.

This was happening because the BLR didn't have a use of the X0 arg register,
which would end up being re-used in high reg pressure situations.
The change also avoids hard coding the use of X0 for the sequence except to
copy the value for the call. ld64 should still be able to optimize it.

rdar://65438258


  Commit: 791544422a446131ef41bb3eef1b7318e7a78c2d
      https://github.com/llvm/llvm-project/commit/791544422a446131ef41bb3eef1b7318e7a78c2d
  Author: Amara Emerson <amara at apple.com>
  Date:   2020-07-21 (Tue, 21 Jul 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
    M llvm/lib/Target/AArch64/AArch64Combine.td
    R llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir

  Log Message:
  -----------
  Revert "[AArch64][GlobalISel] Add post-legalize combine for sext_inreg(trunc(sextload)) -> copy"

This reverts commit 64eb3a4915f00cca9af4c305a9ff36209003cd7b.

It caused miscompiles with optimizations enabled. Reverting while I investigate.


Compare: https://github.com/llvm/llvm-project/compare/7a669130f70c...791544422a44