[all-commits] [llvm/llvm-project] fd02a8: [analyzer] Add system header simulator a symmetric...

[Endre Fülöp via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: fd02a86260b3fb01361175af9600d53354631fb2
      https://github.com/llvm/llvm-project/commit/fd02a86260b3fb01361175af9600d53354631fb2
  Author: Endre Fülöp <endre.fulop at sigmatechnology.se>
  Date:   2020-07-17 (Fri, 17 Jul 2020)

  Changed paths:
    M clang/test/Analysis/Inputs/system-header-simulator-cxx.h
    M clang/test/Analysis/diagnostics/explicit-suppression.cpp

  Log Message:
  -----------
  [analyzer] Add system header simulator a symmetric random access iterator operator+

Summary:
Random access iterators must handle operator+, where the iterator is on the
RHS. The system header simulator library is extended with these operators.

Reviewers: Szelethus

Subscribers: whisperity, xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, Charusso, steakhal, martong, ASDenysPetrov, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D83226