[all-commits] [llvm/llvm-project] 62fd7f: [MachineScheduler] Fix the TopDepth/BotHeightReduc...

Fri Jul 17 03:02:49 PDT 2020

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 62fd7f767c4151b4ec3f4f703e73a27c52f5315c
      https://github.com/llvm/llvm-project/commit/62fd7f767c4151b4ec3f4f703e73a27c52f5315c
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-07-17 (Fri, 17 Jul 2020)

  Changed paths:
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
    M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/bitreverse.ll
    M llvm/test/CodeGen/AMDGPU/bswap.ll
    M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
    M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    M llvm/test/CodeGen/AMDGPU/idot2.ll
    M llvm/test/CodeGen/AMDGPU/idot4s.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8s.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
    M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
    M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/madak.ll
    M llvm/test/CodeGen/AMDGPU/max.i16.ll
    M llvm/test/CodeGen/AMDGPU/memory_clause.ll
    M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/saddo.ll
    M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
    M llvm/test/CodeGen/AMDGPU/sdiv.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/AMDGPU/sign_extend.ll
    M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
    M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
    M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
    M llvm/test/CodeGen/PowerPC/PR33671.ll
    A llvm/test/CodeGen/PowerPC/botheightreduce.mir
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/dform-adjust.ll
    M llvm/test/CodeGen/PowerPC/extract-and-store.ll
    M llvm/test/CodeGen/PowerPC/f128-aggregates.ll
    M llvm/test/CodeGen/PowerPC/f128-conv.ll
    M llvm/test/CodeGen/PowerPC/f128-passByValue.ll
    M llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
    M llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
    M llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
    M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
    M llvm/test/CodeGen/PowerPC/machine-pre.ll
    M llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/pr45432.ll
    M llvm/test/CodeGen/PowerPC/pr45448.ll
    M llvm/test/CodeGen/PowerPC/pr45628.ll
    M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
    M llvm/test/CodeGen/PowerPC/recipest.ll
    M llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll
    M llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll
    M llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
    M llvm/test/CodeGen/PowerPC/sched-addi.ll
    M llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
    M llvm/test/CodeGen/PowerPC/sms-grp-order.ll
    M llvm/test/CodeGen/PowerPC/sms-phi-3.ll
    M llvm/test/CodeGen/PowerPC/sms-simple.ll
    M llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
    M llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll
    A llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
    M llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
    M llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
    M llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
    M llvm/test/CodeGen/PowerPC/vavg.ll
    M llvm/test/CodeGen/PowerPC/vec-bswap.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/X86/testb-je-fusion.ll
    A llvm/test/CodeGen/X86/topdepthreduce-postra.mir

  Log Message:
  -----------
  [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics

tryLatency compares two sched candidates. For the top zone it prefers
the one with lesser depth, but only if that depth is greater than the
total latency of the instructions we've already scheduled -- otherwise
its latency would be hidden and there would be no stall.

Unfortunately it only tests the depth of one of the candidates. This can
lead to situations where the TopDepthReduce heuristic does not kick in,
but a lower priority heuristic chooses the other candidate, whose depth
*is* greater than the already scheduled latency, which causes a stall.

The fix is to apply the heuristic if the depth of *either* candidate is
greater than the already scheduled latency.

All this also applies to the BotHeightReduce heuristic in the bottom
zone.

Differential Revision: https://reviews.llvm.org/D72392