[all-commits] [llvm/llvm-project] b9a6fb: [ARM] VBIT/VBIF support added.

[Pavel Iliin via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b9a6fb64281b6836e565ee39fb0d543bf184fd88
      https://github.com/llvm/llvm-project/commit/b9a6fb64281b6836e565ee39fb0d543bf184fd88
  Author: Pavel Iliin <Pavel.Iliin at arm.com>
  Date:   2020-07-16 (Thu, 16 Jul 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrNEON.td
    M llvm/lib/Target/ARM/ARMScheduleA57.td
    M llvm/lib/Target/ARM/ARMScheduleR52.td
    M llvm/lib/Target/ARM/ARMScheduleSwift.td
    M llvm/test/CodeGen/ARM/fcopysign.ll
    M llvm/test/CodeGen/ARM/fp16-promote.ll
    M llvm/test/CodeGen/ARM/vbsl-constant.ll
    M llvm/test/CodeGen/ARM/vbsl.ll
    M llvm/test/CodeGen/ARM/vselect_imax.ll
    M llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll
    M llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll
    M llvm/test/MC/ARM/neon-bitwise-encoding.s
    M llvm/test/MC/ARM/neont2-bitwise-encoding.s
    M llvm/test/MC/Disassembler/ARM/neon-tests.txt
    M llvm/test/MC/Disassembler/ARM/neon.txt
    M llvm/test/MC/Disassembler/ARM/neont2.txt

  Log Message:
  -----------
  [ARM] VBIT/VBIF support added.

Vector bitwise selects are matched by pseudo VBSP instruction
and expanded to VBSL/VBIT/VBIF after register allocation
depend on operands registers to minimize extra copies.