[all-commits] [llvm/llvm-project] c1d021: [NFC][RISCV] Test for D81805

[Roger Ferrer Ibáñez via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c1d021e2cc9f51503fa4510cb90103b8152f5ccb
      https://github.com/llvm/llvm-project/commit/c1d021e2cc9f51503fa4510cb90103b8152f5ccb
  Author: Roger Ferrer Ibanez <roger.ferrer at bsc.es>
  Date:   2020-07-14 (Tue, 14 Jul 2020)

  Changed paths:
    A llvm/test/CodeGen/RISCV/stack-store-check.ll

  Log Message:
  -----------
  [NFC][RISCV] Test for D81805

New test to show the changes after D81805 is committed.

Differential Revision: https://reviews.llvm.org/D83750


  Commit: 0cbdd2a82ad84dc9c70341a8900506cc5676edfe
      https://github.com/llvm/llvm-project/commit/0cbdd2a82ad84dc9c70341a8900506cc5676edfe
  Author: Roger Ferrer Ibanez <roger.ferrer at bsc.es>
  Date:   2020-07-14 (Tue, 14 Jul 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/stack-store-check.ll

  Log Message:
  -----------
  [RISCV] Fix isStoreToStackSlot

Because of the layout of stores (that don't have a destination operand)
this check is exactly the same as the one in
RISCVInstrInfo::isLoadFromStackSlot.

Differential Revision: https://reviews.llvm.org/D81805


Compare: https://github.com/llvm/llvm-project/compare/3d0b76022df6...0cbdd2a82ad8