[all-commits] [llvm/llvm-project] 2df46a: [DAGCombiner] allow load/store merging if pairs ca...

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  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2df46a574387663717a352eebad017979d3b5ef4
      https://github.com/llvm/llvm-project/commit/2df46a574387663717a352eebad017979d3b5ef4
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/merge-store-dependency.ll
    M llvm/test/CodeGen/X86/stores-merging.ll

  Log Message:
  -----------
  [DAGCombiner] allow load/store merging if pairs can be rotated into place

This carves out an exception for a pair of consecutive loads that are
reversed from the consecutive order of a pair of stores. All of the
existing profitability/legality checks for the memops remain between
the 2 altered hunks of code.

This should give us the same x86 base-case asm that gcc gets in
PR41098 and PR44895:
http://bugs.llvm.org/PR41098
http://bugs.llvm.org/PR44895

I think we are missing a potential subsequent conversion to use "movbe"
if the target supports that. That might be similar to what AArch64
would use to get "rev16".

Differential Revision: https://reviews.llvm.org/D83567