[all-commits] [llvm/llvm-project] 5ffec4: [PowerPC][Power10] Add Instruction definition/MC T...

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  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5ffec467202808f92c378adae95d9972926aba7d
      https://github.com/llvm/llvm-project/commit/5ffec467202808f92c378adae95d9972926aba7d
  Author: Albion Fung <albionapc at gmail.com>
  Date:   2020-07-09 (Thu, 09 Jul 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    M llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
    M llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

  Log Message:
  -----------
  [PowerPC][Power10] Add Instruction definition/MC Tests for Load/Store Rightmost VSX Vector

This patch adds the instruction definitions and the assembly/disassembly
tests for the Load/Store VSX Vector Rightmose instructions.

Differential Revision: https://reviews.llvm.org/D83364