[all-commits] [llvm/llvm-project] 3e7591: [X86] Directly emit X86ISD::BLENDV instead of VSEL...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e75912005cbbdc7c7244b73319cb7441e64682f
      https://github.com/llvm/llvm-project/commit/3e75912005cbbdc7c7244b73319cb7441e64682f
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-07-09 (Thu, 09 Jul 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp

  Log Message:
  -----------
  [X86] Directly emit X86ISD::BLENDV instead of VSELECT in a few places that were emitting sign bit tests.

Technically a VSELECT expects a vector of all 1s or 0s elements
for its condition. But we aren't guaranteeing that the sign bit
and the non sign bits match in these locations. So we should use
BLENDV which is more relaxed.

Differential Revision: https://reviews.llvm.org/D83447