[all-commits] [llvm/llvm-project] fb7545: [SVE] Custom ISel for fixed length extract/insert_...

[paulwalker-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: fb75451775f83c04d53e4e94bb4bd298ea9a882f
      https://github.com/llvm/llvm-project/commit/fb75451775f83c04d53e4e94bb4bd298ea9a882f
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2020-07-08 (Wed, 08 Jul 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    A llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll

  Log Message:
  -----------
  [SVE] Custom ISel for fixed length extract/insert_subvector.

We use extact_subvector and insert_subvector to "cast" between
fixed length and scalable vectors.  This patch adds custom c++
based ISel for the following cases:

  fixed_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0
  scalable_vector = ISD::INSERT_SUBVECTOR undef(scalable_vector), fixed_vector, 0

Which result in either EXTRACT_SUBREG/INSERT_SUBREG for NEON sized
vectors or COPY_TO_REGCLASS otherwise.

Differential Revision: https://reviews.llvm.org/D82871