[all-commits] [llvm/llvm-project] 5e8084: [SVE][CodeGen] Legalisation of unpredicated load i...

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5e8084beba20f27ce14536168087e5c6971e292d
      https://github.com/llvm/llvm-project/commit/5e8084beba20f27ce14536168087e5c6971e292d
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2020-07-07 (Tue, 07 Jul 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    A llvm/test/CodeGen/AArch64/sve-split-load.ll

  Log Message:
  -----------
  [SVE][CodeGen] Legalisation of unpredicated load instructions

Summary:
When splitting a load of a scalable type, the new address is
calculated in SplitVecRes_LOAD using a vscale and an add instruction.

This patch also adds a DAG combiner fold to visitADD for vscale:
 - Fold (add (vscale(C0)), (vscale(C1))) to (add (vscale(C0 + C1)))

Reviewers: sdesmalen, efriedma, david-arm

Reviewed By: david-arm

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82792