[all-commits] [llvm/llvm-project] 61c2a0: [RISCV] Fold ADDIs into load/stores with nonzero o...

[Luís Marques via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 61c2a0bb823677ce0e604b92e5dae65d9bd32b6e
      https://github.com/llvm/llvm-project/commit/61c2a0bb823677ce0e604b92e5dae65d9bd32b6e
  Author: Luís Marques <luismarques at lowrisc.org>
  Date:   2020-07-06 (Mon, 06 Jul 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/RISCV/fp128.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
    M llvm/test/CodeGen/RISCV/wide-mem.ll

  Log Message:
  -----------
  [RISCV] Fold ADDIs into load/stores with nonzero offsets

We can often fold an ADDI into the offset of load/store instructions:

   (load (addi base, off1), off2) -> (load base, off1+off2)
   (store val, (addi base, off1), off2) -> (store val, base, off1+off2)

This is possible when the off1+off2 continues to fit the 12-bit immediate.
We remove the previous restriction where we would never fold the ADDIs if
the load/stores had nonzero offsets. We now do the fold the the resulting
constant still fits a 12-bit immediate, or if off1 is a variable's address
and we know based on that variable's alignment that off1+offs2 won't overflow.

Differential Revision: https://reviews.llvm.org/D79690