[all-commits] [llvm/llvm-project] bc110d: [SelectionDAG] don't split branch on logic-of-vect...

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  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: bc110de78a4bf47f63267eae07ef02f14bcc78e3
      https://github.com/llvm/llvm-project/commit/bc110de78a4bf47f63267eae07ef02f14bcc78e3
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/test/CodeGen/AArch64/vec-extract-branch.ll
    M llvm/test/CodeGen/X86/setcc-logic.ll

  Log Message:
  -----------
  [SelectionDAG] don't split branch on logic-of-vector-compares

SelectionDAGBuilder converts logic-of-compares into multiple branches based
on a boolean TLI setting in isJumpExpensive(). But that probably never
considered the pattern of extracted bools from a vector compare - it seems
unlikely that we would want to turn vector logic into control-flow.

The motivating x86 reduction case is shown in PR44565:
https://bugs.llvm.org/show_bug.cgi?id=44565
...and that test shows the expected improvement from using pmovmsk codegen.

For AArch64, I modified the test to include an extra op because the simpler
test gets transformed by a codegen invocation of SimplifyCFG.

Differential Revision: https://reviews.llvm.org/D82602