[all-commits] [llvm/llvm-project] a230f1: AMDGPU: Fix missing tracksRegLiveness in tests

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a230f1db3f2a4c661308837859a4ed0513a9ceee
      https://github.com/llvm/llvm-project/commit/a230f1db3f2a4c661308837859a4ed0513a9ceee
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-07-01 (Wed, 01 Jul 2020)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir

  Log Message:
  -----------
  AMDGPU: Fix missing tracksRegLiveness in tests

I have no idea why this is considered optional, or why it's not the
default. Also add uses of the copied registers for more useful
liveness testing.


  Commit: afb3bd9914fd39476630dcb521496cfbff7e12c9
      https://github.com/llvm/llvm-project/commit/afb3bd9914fd39476630dcb521496cfbff7e12c9
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-07-01 (Wed, 01 Jul 2020)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocGreedy.cpp

  Log Message:
  -----------
  RegAllocGreedy: Use TargetInstrInfo already in the class


  Commit: d2e74fad20bf8cf66ff20a43fe2934d71e046528
      https://github.com/llvm/llvm-project/commit/d2e74fad20bf8cf66ff20a43fe2934d71e046528
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-07-01 (Wed, 01 Jul 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
    A llvm/test/CodeGen/AMDGPU/agpr-remat.ll
    M llvm/test/CodeGen/AMDGPU/spill-agpr.ll

  Log Message:
  -----------
  AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32

This fixes extra copies when materializing constants in AGPRs. This
made it a lot harder to trigger the spilling in spill-agpr.ll


Compare: https://github.com/llvm/llvm-project/compare/54e2dc7537dd...d2e74fad20bf