[all-commits] [llvm/llvm-project] 4b0aa5: Change the INLINEASM_BR MachineInstr to be a non-t...

[James Y Knight via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 4b0aa5724feaa89a9538dcab97e018110b0e4bc3
      https://github.com/llvm/llvm-project/commit/4b0aa5724feaa89a9538dcab97e018110b0e4bc3
  Author: James Y Knight <jyknight at google.com>
  Date:   2020-07-01 (Wed, 01 Jul 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/include/llvm/CodeGen/MachineBasicBlock.h
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/CodeGen/BranchFolding.cpp
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/PHIEliminationUtils.cpp
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/ShrinkWrap.cpp
    M llvm/lib/CodeGen/SplitKit.cpp
    M llvm/lib/CodeGen/SplitKit.h
    M llvm/lib/CodeGen/TailDuplicator.cpp
    M llvm/lib/CodeGen/TargetInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/Hexagon/BitTracker.cpp
    M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
    M llvm/test/CodeGen/AArch64/callbr-asm-label.ll
    M llvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll
    M llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
    M llvm/test/CodeGen/ARM/ifcvt-size.mir
    M llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
    M llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
    A llvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll
    M llvm/test/CodeGen/X86/callbr-asm-label-addr.ll
    M llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll
    M llvm/test/CodeGen/X86/callbr-asm-outputs.ll
    M llvm/test/CodeGen/X86/callbr-asm.ll
    A llvm/test/CodeGen/X86/shrinkwrap-callbr.ll
    M llvm/test/Verifier/callbr.ll

  Log Message:
  -----------
  Change the INLINEASM_BR MachineInstr to be a non-terminating instruction.

Before this instruction supported output values, it fit fairly
naturally as a terminator. However, being a terminator while also
supporting outputs causes some trouble, as the physreg->vreg COPY
operations cannot be in the same block.

Modeling it as a non-terminator allows it to be handled the same way
as invoke is handled already.

Most of the changes here were created by auditing all the existing
users of MachineBasicBlock::isEHPad() and
MachineBasicBlock::hasEHPadSuccessor(), and adding calls to
isInlineAsmBrIndirectTarget or mayHaveInlineAsmBr, as appropriate.

Reviewed By: nickdesaulniers, void

Differential Revision: https://reviews.llvm.org/D79794