[all-commits] [llvm/llvm-project] d36f2c: [RISCV] Add mcountinhibit CSR

[pzhengqc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d36f2c6a6c4bb3c1cd213f3ed08a7a090fee54d2
      https://github.com/llvm/llvm-project/commit/d36f2c6a6c4bb3c1cd213f3ed08a7a090fee54d2
  Author: Pengxuan Zheng <pzheng at quicinc.com>
  Date:   2020-07-01 (Wed, 01 Jul 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/MC/RISCV/machine-csr-names.s

  Log Message:
  -----------
  [RISCV] Add mcountinhibit CSR

Summary:
The mcountinhibit CSR is defined in the ratified 1.11 version of the privileged
spec.

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82913