[all-commits] [llvm/llvm-project] a7b0f3: [MVT] Add new MVT types for RISC-V vector.

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a7b0f391852b6dd9001b5247269612b3d2c3ce31
      https://github.com/llvm/llvm-project/commit/a7b0f391852b6dd9001b5247269612b3d2c3ce31
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-07-01 (Wed, 01 Jul 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/include/llvm/Support/MachineValueType.h
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/utils/TableGen/CodeGenTarget.cpp

  Log Message:
  -----------
  [MVT] Add new MVT types for RISC-V vector.

In RISC-V vector extension, users could group multiple vector registers
as one pseudo register. In mixed width operations, users could use
partial vector registers to reduce the register pressure. The parameter
to control register grouping and partial use is called LMUL. LMUL is a
part of the type. So, we have a bunch of vector types. In order to
support all these types, we need new MVT types in LLVM. In this patch, I
added several MVT types that are used in RISC-V vector implementation.
This is a standalone patch for MVT types without RISC-V related implementation.

Differential revision: https://reviews.llvm.org/D81724