[all-commits] [llvm/llvm-project] 3521ec: [X86] Add vector support to targetShrinkDemandedCo...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3521ecf1f8a3cf5e4811f93a9a809fc722462bbf
      https://github.com/llvm/llvm-project/commit/3521ecf1f8a3cf5e4811f93a9a809fc722462bbf
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-06-29 (Mon, 29 Jun 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/promote-cmp.ll
    M llvm/test/CodeGen/X86/setcc-lowering.ll

  Log Message:
  -----------
  [X86] Add vector support to targetShrinkDemandedConstant for OR/XOR opcodes

If a constant is only allsignbits in the demanded/active bits, then sign extend it to an allsignbits bool pattern for OR/XOR ops.

This also requires SimplifyDemandedBits XOR handling to be modified to call ShrinkDemandedConstant on any (non-NOT) XOR pattern to account for non-splat cases.

Next step towards fixing PR45808 - with this patch we now get a <-1,-1,0,0> v4i64 constant instead of <1,1,0,0>.

Differential Revision: https://reviews.llvm.org/D82257