[all-commits] [llvm/llvm-project] 66da87: [RISCV] Assemble/Disassemble v-ext instructions.

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 66da87dcbaf91fa3393ce80c687e9c2d133ee3ca
      https://github.com/llvm/llvm-project/commit/66da87dcbaf91fa3393ce80c687e9c2d133ee3ca
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-06-28 (Sun, 28 Jun 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    A llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket32.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket64.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
    A llvm/test/MC/RISCV/rvv/add.s
    A llvm/test/MC/RISCV/rvv/and.s
    A llvm/test/MC/RISCV/rvv/clip.s
    A llvm/test/MC/RISCV/rvv/compare.s
    A llvm/test/MC/RISCV/rvv/convert.s
    A llvm/test/MC/RISCV/rvv/div.s
    A llvm/test/MC/RISCV/rvv/fadd.s
    A llvm/test/MC/RISCV/rvv/fcompare.s
    A llvm/test/MC/RISCV/rvv/fdiv.s
    A llvm/test/MC/RISCV/rvv/fmacc.s
    A llvm/test/MC/RISCV/rvv/fminmax.s
    A llvm/test/MC/RISCV/rvv/fmul.s
    A llvm/test/MC/RISCV/rvv/fmv.s
    A llvm/test/MC/RISCV/rvv/fothers.s
    A llvm/test/MC/RISCV/rvv/freduction.s
    A llvm/test/MC/RISCV/rvv/fsub.s
    A llvm/test/MC/RISCV/rvv/invalid.s
    A llvm/test/MC/RISCV/rvv/load.s
    A llvm/test/MC/RISCV/rvv/macc.s
    A llvm/test/MC/RISCV/rvv/mask.s
    A llvm/test/MC/RISCV/rvv/minmax.s
    A llvm/test/MC/RISCV/rvv/mul.s
    A llvm/test/MC/RISCV/rvv/mv.s
    A llvm/test/MC/RISCV/rvv/or.s
    A llvm/test/MC/RISCV/rvv/others.s
    A llvm/test/MC/RISCV/rvv/reduction.s
    A llvm/test/MC/RISCV/rvv/shift.s
    A llvm/test/MC/RISCV/rvv/sign-injection.s
    A llvm/test/MC/RISCV/rvv/snippet.s
    A llvm/test/MC/RISCV/rvv/store.s
    A llvm/test/MC/RISCV/rvv/sub.s
    A llvm/test/MC/RISCV/rvv/vsetvl.s
    A llvm/test/MC/RISCV/rvv/xor.s

  Log Message:
  -----------
  [RISCV] Assemble/Disassemble v-ext instructions.

Assemble/disassemble RISC-V V extension instructions according to
latest version spec in https://github.com/riscv/riscv-v-spec/.

I have tested this patch using GNU toolchain. The encoding is aligned
to GNU assembler output. In this patch, there is a test case for each
instruction at least.

The V register definition is just for assemble/disassemble. Its type
is not important in this stage. I think it will be reviewed and modified
as we want to do codegen for scalable vector types.

This patch does not include Zvamo, Zvlsseg, and Zvediv.

Differential revision: https://reviews.llvm.org/D69987


  Commit: d698ff92a59c0632aa6a88b72890eb401bd64faa
      https://github.com/llvm/llvm-project/commit/d698ff92a59c0632aa6a88b72890eb401bd64faa
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-06-28 (Sun, 28 Jun 2020)

  Changed paths:
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-arch.c

  Log Message:
  -----------
  [RISCV] Support experimental v extensions.

This follows the design as discussed on the mailing lists in the
following RFC:
http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html

Support for the vector 'v' extension v0.8.

Differential revision: https://reviews.llvm.org/D81188


Compare: https://github.com/llvm/llvm-project/compare/f0634100cdc8...d698ff92a59c