[all-commits] [llvm/llvm-project] d56c64: [X86][AVX] SimplifyDemandedVectorEltsForTargetNode...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d56c6475a60aa44b040983fe4fd355399cc4c42d
      https://github.com/llvm/llvm-project/commit/d56c6475a60aa44b040983fe4fd355399cc4c42d
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-06-27 (Sat, 27 Jun 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/var-permute-256.ll

  Log Message:
  -----------
  [X86][AVX] SimplifyDemandedVectorEltsForTargetNode - reduce width of X86ISD::VPERMILPV

If we don't need the elements of the upper lanes, reduce the width of the X86ISD::VPERMILPV node.


  Commit: e855efe42407dd67f6a513927d0669cb7a66f448
      https://github.com/llvm/llvm-project/commit/e855efe42407dd67f6a513927d0669cb7a66f448
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-06-27 (Sat, 27 Jun 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/var-permute-256.ll

  Log Message:
  -----------
  [X86][AVX] SimplifyDemandedVectorEltsForTargetNode - reduce width of X86ISD::VPERMIL2

If we don't need the elements of the upper lanes, reduce the width of the X86ISD::VPERMIL2 node.


Compare: https://github.com/llvm/llvm-project/compare/a43b99a1e38e...e855efe42407