[all-commits] [llvm/llvm-project] 3a98d5: [SVE] Code generation for fixed length vector adds.

[paulwalker-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3a98d5d7e7f5c651f1f22bf8dc552d5161cb999e
      https://github.com/llvm/llvm-project/commit/3a98d5d7e7f5c651f1f22bf8dc552d5161cb999e
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
    A llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll

  Log Message:
  -----------
  [SVE] Code generation for fixed length vector adds.

Summary:
Teach LowerToPredicatedOp to lower fixed length vector operations.

Add AArch64ISD nodes and isel patterns for predicated integer
and floating point adds.

Together this enables SVE code generation for fixed length vector adds.

Reviewers: rengolin, efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82483