[all-commits] [llvm/llvm-project] 76e0e1: [ARM] VCVTT instruction selection

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 76e0e1a55d1ccecebbd98fb1fa5c7ab5a4f013cc
      https://github.com/llvm/llvm-project/commit/76e0e1a55d1ccecebbd98fb1fa5c7ab5a4f013cc
  Author: David Green <david.green at arm.com>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrNEON.td
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/test/CodeGen/ARM/fp16-insert-extract.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-div-expand.ll
    M llvm/test/CodeGen/Thumb2/mve-fmath.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
    M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

  Log Message:
  -----------
  [ARM] VCVTT instruction selection

We current extract and convert from a top lane of a f16 vector using a
VMOVX;VCVTB pair. We can simplify that to use a single VCVTT. The
pattern is mostly copied from a vector extract pattern, but produces a
VCVTTHS f32 directly.

This had to move some code around so that ARMInstrVFP had access to the
required pattern frags that were previously part of ARMInstrNEON.

Differential Revision: https://reviews.llvm.org/D81556