[all-commits] [llvm/llvm-project] 3cb219: [ARM] MVE VCVT lowering for f32->f16 truncs

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3cb2190b0ba3f54d6b540ba8ba44f5c26c6e898f
      https://github.com/llvm/llvm-project/commit/3cb2190b0ba3f54d6b540ba8ba44f5c26c6e898f
  Author: David Green <david.green at arm.com>
  Date:   2020-06-25 (Thu, 25 Jun 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll
    M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

  Log Message:
  -----------
  [ARM] MVE VCVT lowering for f32->f16 truncs

This adds code to lower f32 to f16 fp_trunc's using a pair of MVE VCVT
instructions. Due to v4f16 not being legal, fp_round are often split up
fairly early. So this reconstructs the vcvt's from a buildvector of
fp_rounds from two vector inputs. Something like:

BUILDVECTOR(FP_ROUND(EXTRACT_ELT(X, 0),
            FP_ROUND(EXTRACT_ELT(Y, 0),
            FP_ROUND(EXTRACT_ELT(X, 1),
            FP_ROUND(EXTRACT_ELT(Y, 1), ...)

It adds a VCVTN node to handle this, which like VMOVN or VQMOVN lowers
into the top/bottom lanes of an MVE instruction.

Differential Revision: https://reviews.llvm.org/D81139