[all-commits] [llvm/llvm-project] e9d4e3: [AArch64][SVE] Add legalization support for i32/i6...

[Eli Friedman via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e9d4e34ab8a4223de41fbf1881fd6a531880dda9
      https://github.com/llvm/llvm-project/commit/e9d4e34ab8a4223de41fbf1881fd6a531880dda9
  Author: Eli Friedman <efriedma at quicinc.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll

  Log Message:
  -----------
  [AArch64][SVE] Add legalization support for i32/i64 vector srem/urem

Implement them on top of sdiv/udiv, similar to what we do for integer
types.

Potential future work: implementing i8/i16 srem/urem, optimizations for
constant divisors, optimizing the mul+sub to mls.

Differential Revision: https://reviews.llvm.org/D81511