[all-commits] [llvm/llvm-project] 499c63: [SVE] Code generation for fixed length vector load...

[paulwalker-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 499c63288f4e3385e8d7311b214fb4f743e33234
      https://github.com/llvm/llvm-project/commit/499c63288f4e3385e8d7311b214fb4f743e33234
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    A llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll
    A llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll

  Log Message:
  -----------
  [SVE] Code generation for fixed length vector loads & stores.

Summary:
This patch adds base support for code generating fixed length
vector operations targeting a known SVE vector length. To achieve
this we lower fixed length vector operations to equivalent scalable
vector operations, whereby SVE predication is used to limit the
elements processed to those present within the fixed length vector.

Specifically this patch implements load and store operations, which
get lowered to their masked counterparts thusly:

  V = load(Addr) =>
    V = extract_fixed_vector(masked_load(make_pred(V.NumElts), Addr))

  store(V, (Addr)) =>
    masked_store(insert_fixed_vector(V), make_pred(V.NumElts), Addr))

Reviewers: rengolin, efriedma

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80385