[all-commits] [llvm/llvm-project] ff4817: [AVR] Don't adjust for instruction size

[Ayke via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ff4817ec2adb1e716051c286bcdc5ef4d1b32dd3
      https://github.com/llvm/llvm-project/commit/ff4817ec2adb1e716051c286bcdc5ef4d1b32dd3
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
    A llvm/test/CodeGen/AVR/jmp-long.ll

  Log Message:
  -----------
  [AVR] Don't adjust for instruction size

I'm not entirely sure why this was ever needed, but when I remove both
adjustments all tests still pass.

This fixes a bug where a long branch (using the `jmp` instead of the
`rjmp` instruction) was incorrectly adjusted by 2 because it jumps to an
absolute address instead of a PC-relative address. I could have added
AVR::fixup_call to the list of exceptions, but it seemed more sensible
to me to just remove this code.

Differential Revision: https://reviews.llvm.org/D78459


  Commit: 01c2209d518c7f19de7997ac29385c699a7ccd35
      https://github.com/llvm/llvm-project/commit/01c2209d518c7f19de7997ac29385c699a7ccd35
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AVR/AVRInstrFormats.td
    M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
    M llvm/test/MC/AVR/inst-asr.s
    M llvm/test/MC/AVR/inst-com.s
    M llvm/test/MC/AVR/inst-dec.s
    M llvm/test/MC/AVR/inst-inc.s
    M llvm/test/MC/AVR/inst-lsr.s
    M llvm/test/MC/AVR/inst-neg.s
    M llvm/test/MC/AVR/inst-pop.s
    M llvm/test/MC/AVR/inst-push.s
    M llvm/test/MC/AVR/inst-ror.s
    M llvm/test/MC/AVR/inst-swap.s

  Log Message:
  -----------
  [AVR] Decode single register instructions

This is a set of instructions that take just a single register as an
operand, with no immediates. Because all instructions share the same
format, I haven't added exhaustive bit testing to all instructions but
just to the inc instruction.

Differential Revision: https://reviews.llvm.org/D81968


  Commit: ec9efb856c6f3c764c921cee3900eab48f0fc076
      https://github.com/llvm/llvm-project/commit/ec9efb856c6f3c764c921cee3900eab48f0fc076
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AVR/AVRInstrFormats.td
    M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
    M llvm/test/MC/AVR/inst-fmul.s
    M llvm/test/MC/AVR/inst-fmuls.s
    M llvm/test/MC/AVR/inst-fmulsu.s
    M llvm/test/MC/AVR/inst-muls.s
    M llvm/test/MC/AVR/inst-mulsu.s

  Log Message:
  -----------
  [AVR] Disassemble multiplication instructions

These can often only use a limited range of registers, and apparently
need special decoding support.

Differential Revision: https://reviews.llvm.org/D81971


  Commit: 9f09c29f0158f59dad07bce11e67470c0399c259
      https://github.com/llvm/llvm-project/commit/9f09c29f0158f59dad07bce11e67470c0399c259
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AVR/AVRInstrFormats.td
    M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
    M llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
    M llvm/test/MC/AVR/inst-elpm.s
    M llvm/test/MC/AVR/inst-lac.s
    M llvm/test/MC/AVR/inst-las.s
    M llvm/test/MC/AVR/inst-lat.s
    M llvm/test/MC/AVR/inst-lpm.s
    M llvm/test/MC/AVR/inst-spm.s
    M llvm/test/MC/AVR/inst-xch.s

  Log Message:
  -----------
  [AVR] Disassemble instructions with fixed Z operand

Some instructions have a fixed Z register and don't have an explicit
register operand. This can be worked around by simply printing the
operand directly if the particular register class is detected.

The LPM and ELPM instructions also needed a custom decoder, which is
also included in this patch.

Differential Revision: https://reviews.llvm.org/D82088


  Commit: eac4a601548566fb311b0b596dbaee893507cfb8
      https://github.com/llvm/llvm-project/commit/eac4a601548566fb311b0b596dbaee893507cfb8
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AVR/AVRInstrFormats.td
    M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
    M llvm/test/MC/AVR/inst-adiw.s
    M llvm/test/MC/AVR/inst-movw.s
    M llvm/test/MC/AVR/inst-sbiw.s

  Log Message:
  -----------
  [AVR] Disassemble double register instructions

Add disassembly support for the movw, adiw, and sbiw instructions.

I had previously committed test cases for the adiw and sbiw
instructions, but had accidentally made them not runnable so they were
skipped all this time. Oops. This patch fixes that by adding support for
disassembling those instructions.

Differential Revision: https://reviews.llvm.org/D82093


Compare: https://github.com/llvm/llvm-project/compare/d332ec9209ac...eac4a6015485