[all-commits] [llvm/llvm-project] 584d0d: [SVE] Fall back on DAG ISel at -O0 when encounteri...

[david-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 584d0d5c1749c13625a5d322178ccb4121eea610
      https://github.com/llvm/llvm-project/commit/584d0d5c1749c13625a5d322178ccb4121eea610
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll

  Log Message:
  -----------
  [SVE] Fall back on DAG ISel at -O0 when encountering scalable types

At the moment we use Global ISel by default at -O0, however it is
currently not capable of dealing with scalable vectors for two
reasons:

1. The register banks know nothing about SVE registers.
2. The LLT (Low Level Type) class knows nothing about scalable
   vectors.

For now, the easiest way to avoid users hitting issues when using
the SVE ACLE is to fall back on normal DAG ISel when encountering
instructions that operate on scalable vector types.

I've added a couple of RUN lines to existing SVE tests to ensure
we can compile at -O0. I've also added some new tests to

  CodeGen/AArch64/GlobalISel/arm64-fallback.ll

that demonstrate we correctly fallback to DAG ISel at -O0 when
lowering formal arguments or translating instructions that involve
scalable vector types.

Differential Revision: https://reviews.llvm.org/D81557