[all-commits] [llvm/llvm-project] d938ec: [AArch64] Avoid incompatibility between SLSBLR mit...

[Kristof Beyls via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d938ec4509c47d461377527fc2877ae14b91275c
      https://github.com/llvm/llvm-project/commit/d938ec4509c47d461377527fc2877ae14b91275c
  Author: Kristof Beyls <kristof.beyls at arm.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
    M llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll

  Log Message:
  -----------
  [AArch64] Avoid incompatibility between SLSBLR mitigation and BTI codegen.

A "BTI c" instruction only allows jumping/calling to using a BLR* instruction.
However, the SLSBLR mitigation changes a BLR to a BR to implement the
function call. Therefore, a "BTI c" check that passed before could
trigger after the BLR->BL change done by the SLSBLR mitigation.
However, if the register used in BR is X16 or X17, this trigger will not
fire (see ArmARM for further details).

Therefore, this patch simply changes the function stubs for the SLSBLR
mitigation from
__llvm_slsblr_thunk_x<N>:
    br x<N>
    SpeculationBarrier
to
__llvm_slsblr_thunk_x<N>:
    mov x16, x<N>
    br  x16
    SpeculationBarrier

Differential Revision: https://reviews.llvm.org/D81405