[all-commits] [llvm/llvm-project] b4c914: [AVR] Fix miscompilation of zext + add

[Ayke via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b4c91462e84e66684c09d36c3c4ee9a10b9cb2cb
      https://github.com/llvm/llvm-project/commit/b4c91462e84e66684c09d36c3c4ee9a10b9cb2cb
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2020-06-18 (Thu, 18 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AVR/AVRInstrInfo.td
    M llvm/test/CodeGen/AVR/add.ll

  Log Message:
  -----------
  [AVR] Fix miscompilation of zext + add

Code like the following:

    define i32 @foo(i32 %a, i1 zeroext %b) addrspace(1) {
    entry:
      %conv = zext i1 %b to i32
      %add = add nsw i32 %conv, %a
      ret i32 %add
    }

Would compile to the following (incorrect) code:

    foo:
        mov     r18, r20
        clr     r19
        add     r22, r18
        adc     r23, r19
        sbci    r24, 0
        sbci    r25, 0
        ret

Those sbci instructions are clearly wrong, they should have been adc
instructions.

This commit improves codegen to use adc instead:

    foo:
        mov     r18, r20
        clr     r19
        ldi     r20, 0
        ldi     r21, 0
        add     r22, r18
        adc     r23, r19
        adc     r24, r20
        adc     r25, r21
        ret

This code is not optimal (it could be just 5 instructions instead of the
current 9) but at least it doesn't miscompile.

Differential Revision: https://reviews.llvm.org/D78439