[all-commits] [llvm/llvm-project] 320907: [X86] make sure POP has implicit def/use of stack ...

[Wei Zhao via All-commits]

  Branch: refs/heads/release/10.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 320907788da95386189be35c4480cb35ce896e8e
      https://github.com/llvm/llvm-project/commit/320907788da95386189be35c4480cb35ce896e8e
  Author: Yuanfang Chen <yuanfang.chen at sony.com>
  Date:   2020-06-17 (Wed, 17 Jun 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/test/CodeGen/X86/materialize.ll

  Log Message:
  -----------
  [X86] make sure POP has implicit def/use of stack pointer when materializing 8-bit immediates for minsize

Summary:
Otherwise PostRA list scheduler may reorder instruction, such as

schedule this
'''
pushq  $0x8
pop    %rbx
lea    0x2a0(%rsp),%r15
'''
to
'''
pushq  $0x8
lea    0x2a0(%rsp),%r15
pop    %rbx
'''
by mistake. The patch is to prevent this to happen by making sure POP has
implicit use of SP.

Reviewers: craig.topper

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77031

(cherry picked from commit ece79f47083babcabde3700c67b90ef19967a5b3)


  Commit: f5a9c661a35621640370837bae67cfb28f2f279b
      https://github.com/llvm/llvm-project/commit/f5a9c661a35621640370837bae67cfb28f2f279b
  Author: Wei Zhao <wxz at marvell.com>
  Date:   2020-06-17 (Wed, 17 Jun 2020)

  Changed paths:
    M clang/test/Driver/aarch64-cpus.c
    M llvm/include/llvm/Support/AArch64TargetParser.def
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64SchedA53.td
    M llvm/lib/Target/AArch64/AArch64SchedA57.td
    M llvm/lib/Target/AArch64/AArch64SchedCyclone.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    M llvm/lib/Target/AArch64/AArch64SchedFalkor.td
    M llvm/lib/Target/AArch64/AArch64SchedKryo.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
    A llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
    M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    M llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
    M llvm/test/CodeGen/AArch64/cpus.ll
    M llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
    M llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
    M llvm/test/CodeGen/AArch64/remat.ll
    M llvm/unittests/Support/TargetParserTest.cpp

  Log Message:
  -----------
  [AARch64] Add Marvell ThunderX3T110 support

This is the first checkin to support Marvell ThunderX3T110.

Initial definition of the micro-ops of the instructions in ThunderX3T110
is included.

Differential Revision: https://reviews.llvm.org/D78129

(cherry picked from commit 382d3a85e2a9269569e7fb8caa487d7ef57900c6)


Compare: https://github.com/llvm/llvm-project/compare/dc94773a91c8...f5a9c661a356