[all-commits] [llvm/llvm-project] ed67f5: [VectorCombine] scalarize compares with insertelem...

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  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ed67f5e7ab59d378bb09153a0df132333c43c9cb
      https://github.com/llvm/llvm-project/commit/ed67f5e7ab59d378bb09153a0df132333c43c9cb
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
    M llvm/test/Transforms/VectorCombine/X86/scalarize-cmp.ll

  Log Message:
  -----------
  [VectorCombine] scalarize compares with insertelement operand(s)

Generalize scalarization (recently enhanced with D80885)
to allow compares as well as binops.
Similar to binops, we are avoiding scalarization of a loaded
value because that could avoid a register transfer in codegen.
This requires 1 extra predicate that I am aware of: we do not
want to scalarize the condition value of a vector select. That
might also invert a transform that we do in instcombine that
prefers a vector condition operand for a vector select.

I think this is the final step in solving PR37463:
https://bugs.llvm.org/show_bug.cgi?id=37463

Differential Revision: https://reviews.llvm.org/D81661