[all-commits] [llvm/llvm-project] 65c3fa: [X86][SSE] combineVectorSizedSetCCEquality - move ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 65c3fa849b1f5b90485c14c17a406ae5ea0096eb
      https://github.com/llvm/llvm-project/commit/65c3fa849b1f5b90485c14c17a406ae5ea0096eb
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp

  Log Message:
  -----------
  [X86][SSE] combineVectorSizedSetCCEquality - move single Subtarget.hasAVX() use into condition. NFC.

We already have Subtarget.hasSSE2() and Subtarget.useAVX512Regs() in the condition - seems to be a legacy from when we had multiple uses.


  Commit: 057c9c7ee00b7f7696065a3fc26a3df5ce3ebe96
      https://github.com/llvm/llvm-project/commit/057c9c7ee00b7f7696065a3fc26a3df5ce3ebe96
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/pr45378.ll
    M llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll

  Log Message:
  -----------
  [X86][SSE] MatchVectorAllZeroTest - handle OR vector reductions

This patch extends MatchVectorAllZeroTest to handle OR vector reduction patterns where the result is compared against zero.

Fixes PR45378

Differential Revision: https://reviews.llvm.org/D81547


Compare: https://github.com/llvm/llvm-project/compare/7965dd79a3da...057c9c7ee00b