[all-commits] [llvm/llvm-project] 2ca552: AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scal...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ca552322c29b61e8c20a0b31cf452de88d8af1c
      https://github.com/llvm/llvm-project/commit/2ca552322c29b61e8c20a0b31cf452de88d8af1c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-06-15 (Mon, 15 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
    A llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads

These are legal since we can do a 96-bit load on some subtargets, but
this is only for vector loads. If we can't widen the load, it needs to
be broken down once known scalar. For 16-byte alignment, widen to a
128-bit load.