[all-commits] [llvm/llvm-project] dae955: AMDGPU/GlobalISel: Workaround some load/store type...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: dae9554b2b039db403a77461fdb95239d6c06a96
      https://github.com/llvm/llvm-project/commit/dae9554b2b039db403a77461fdb95239d6c06a96
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-06-15 (Mon, 15 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/no-legalize-atomic.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Workaround some load/store type selection patterns

The logic is written for what loads/stores should be selectable. There
are a set of cases that should be selectable, but due to missing MVTs
and/or selection patterns, will fail to select. I think eventually
load/store select patterns should ignore the type and only look at the
value size, but until that happens, bitcast these to equivalent i32
vectors.