[all-commits] [llvm/llvm-project] 0cbe71: [X86] Automatically harden inline assembly RET ins...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0cbe713c69f7c12682855ffd61ecb0d7edc262e3
      https://github.com/llvm/llvm-project/commit/0cbe713c69f7c12682855ffd61ecb0d7edc262e3
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-06-13 (Sat, 13 Jun 2020)

  Changed paths:
    M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    M llvm/test/CodeGen/X86/lvi-hardening-inline-asm.ll

  Log Message:
  -----------
  [X86] Automatically harden inline assembly RET instructions against Load Value Injection (LVI)

Previously, the X86AsmParser would issue a warning whenever a ret instruction is encountered. This patch changes the behavior to automatically transform each ret instruction in an inline assembly stream into:

shlq $0, (%rsp)
lfence
ret

which is secure, according to https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions.

Patch by Scott Constable with some minor changes by Craig Topper.