[all-commits] [llvm/llvm-project] 3dcfd4: [CodeGen] Increase applicability of ffine-grained-...

[Alex Bradbury via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3dcfd482cb17fad2d641c976b822d1fe36dc1359
      https://github.com/llvm/llvm-project/commit/3dcfd482cb17fad2d641c976b822d1fe36dc1359
  Author: Alex Bradbury <asb at lowrisc.org>
  Date:   2020-06-12 (Fri, 12 Jun 2020)

  Changed paths:
    M clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
    M clang/test/CodeGenCXX/finegrain-bitfield-type.cpp

  Log Message:
  -----------
  [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

As pointed out in PR45708, -ffine-grained-bitfield-accesses doesn't
trigger in all cases you think it might for RISC-V. The logic in
CGRecordLowering::accumulateBitFields checks OffsetInRecord is a legal
integer according to the datalayout. RISC targets will typically only
have the native width as a legal integer type so this check will fail
for OffsetInRecord of 8 or 16 when you would expect the transformation
is still worthwhile.

This patch changes the logic to check for an OffsetInRecord of a at
least 1 byte, that fits in a legal integer, and is a power of 2. We
would prefer to query whether native load/store operations are
available, but I don't believe that is possible.

Differential Revision: https://reviews.llvm.org/D79155