[all-commits] [llvm/llvm-project] bd9734: [CodeGen] Let computeKnownBits do something sensib...

[david-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: bd97342a0c2c91cb662488d76517f4666c4bb863
      https://github.com/llvm/llvm-project/commit/bd97342a0c2c91cb662488d76517f4666c4bb863
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2020-06-11 (Thu, 11 Jun 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
    M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-setcc.ll
    M llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp

  Log Message:
  -----------
  [CodeGen] Let computeKnownBits do something sensible for scalable vectors

Until we have a real need for computing known bits for scalable
vectors I have simply changed the code to bail out for now and
pretend we know nothing. I've also fixed up some simple callers of
computeKnownBits too.

Differential Revision: https://reviews.llvm.org/D80437