[all-commits] [llvm/llvm-project] 1ba780: [AVR] Implement disassembly support for I/O instru...

[Ayke via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ba7809793913daae4e15d8ca6acbf80db21816d
      https://github.com/llvm/llvm-project/commit/1ba7809793913daae4e15d8ca6acbf80db21816d
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2020-06-10 (Wed, 10 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AVR/AVRInstrFormats.td
    M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
    M llvm/test/MC/AVR/inst-cbi.s
    M llvm/test/MC/AVR/inst-in.s
    M llvm/test/MC/AVR/inst-out.s
    M llvm/test/MC/AVR/inst-sbi.s
    M llvm/test/MC/AVR/inst-sbic.s
    M llvm/test/MC/AVR/inst-sbis.s

  Log Message:
  -----------
  [AVR] Implement disassembly support for I/O instructions

The in, out, and sbi/cbi family of instructions seem to require a custom
decoder. I'm not exactly sure why and would prefer to convince TableGen
to provide the correct decoders for these, but I can't seem to convince
it to do so. They simply disassemble without any operands.

Differential Revision: https://reviews.llvm.org/D74049