[all-commits] [llvm/llvm-project] cb2d8b: [AArch64][GlobalISel] Select trn1 and trn2

[Jessica Paquette via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: cb2d8b30ad0dc08bb151b922f5a137014ef9fc87
      https://github.com/llvm/llvm-project/commit/cb2d8b30ad0dc08bb151b922f5a137014ef9fc87
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2020-06-09 (Tue, 09 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/AArch64InstrGISel.td
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-trn.mir
    A llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Select trn1 and trn2

Same idea as for zip, uzp, etc. Teach the post-legalizer combiner to recognize
G_SHUFFLE_VECTORs that are trn1/trn2 instructions.

- Add G_TRN1 and G_TRN2
- Port mask matching code from AArch64ISelLowering
- Produce G_TRN1 and G_TRN2 in the post-legalizer combiner
- Select via importer

Add select-trn.mir to test selection.

Add postlegalizer-combiner-trn.mir to test the combine. This is similar to the
existing arm64-trn test.

Note that both of these tests contain things we currently don't legalize.

I figured it would be easier to test these now rather than later, since once
we legalize the G_SHUFFLE_VECTORs, it's not guaranteed that someone will update
the tests.

Differential Revision: https://reviews.llvm.org/D81182