[all-commits] [llvm/llvm-project] c95ba1: [VE] Support control instructions in MC layer

[Kazushi Marukawa via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c95ba11a3d87f1c16e92147c28a779796cf1af99
      https://github.com/llvm/llvm-project/commit/c95ba11a3d87f1c16e92147c28a779796cf1af99
  Author: Kazushi (Jam) Marukawa <marukawa at nec.com>
  Date:   2020-06-08 (Mon, 08 Jun 2020)

  Changed paths:
    M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
    M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
    M llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
    M llvm/lib/Target/VE/VEInstrInfo.td
    M llvm/lib/Target/VE/VERegisterInfo.td
    A llvm/test/MC/VE/FIDCR.s
    A llvm/test/MC/VE/LCR.s
    A llvm/test/MC/VE/LFRSFR.s
    A llvm/test/MC/VE/LPMSPM.s
    A llvm/test/MC/VE/MONC.s
    A llvm/test/MC/VE/NOP.s
    A llvm/test/MC/VE/SCR.s
    A llvm/test/MC/VE/SIC.s
    A llvm/test/MC/VE/SMIR.s
    A llvm/test/MC/VE/TSCR.s

  Log Message:
  -----------
  [VE] Support control instructions in MC layer

Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
control instructions.  Add not defined LPM/SPM/LFR/SFR/SMIR/NOP/LCR/
SCR/TSCR/FIDCR control isntructions newly.  Define MISC registers which
SMIR instruction reads and IC register which SIC instruction reads.
Change asmparser to support Zero, UImm3, and UImm6 operands and MISC
registers.  Change instprinter to support MISC registers also.
Change to use auto to receive dyn_cast also.

Differential Revision: https://reviews.llvm.org/D81370