[all-commits] [llvm/llvm-project] f8eabd: [Power9] Add addi post-ra scheduling heuristic

[QingShan Zhang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f8eabd6d016e85d9fb6714f234eacfe999b60164
      https://github.com/llvm/llvm-project/commit/f8eabd6d016e85d9fb6714f234eacfe999b60164
  Author: QingShan Zhang <qshanz at cn.ibm.com>
  Date:   2020-06-08 (Mon, 08 Jun 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineScheduler.h
    M llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
    M llvm/lib/Target/PowerPC/PPCMachineScheduler.h
    M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
    M llvm/test/CodeGen/PowerPC/pr42492.ll
    A llvm/test/CodeGen/PowerPC/sched-addi.ll
    M llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
    M llvm/test/CodeGen/PowerPC/sms-phi-1.ll
    M llvm/test/CodeGen/PowerPC/sms-simple.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

  Log Message:
  -----------
  [Power9] Add addi post-ra scheduling heuristic

The instruction addi is usually used to post increase the loop indvar, which looks like this:

label_X:
 load x, base(i)
 ...
 y = op x
 ...
 i = addi i, 1
 goto label_X

However, for PowerPC, if there are too many vsx instructions that between y = op x and  i = addi i, 1,
it will use all the hw resource that block the execution of i = addi, i, 1, which result in the stall
of the load instruction in next iteration. So, a heuristic is added to move the addi as early as possible
to have the load hide the latency of vsx instructions, if other heuristic didn't apply to avoid the starve.

Reviewed By: jji

Differential Revision: https://reviews.llvm.org/D80269