[all-commits] [llvm/llvm-project] 7c9a89: [X86] Teach combineVectorShiftImm to constant fold...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 7c9a89fed8f5d53d61fe3a61a2581a7c28b1b6d2
      https://github.com/llvm/llvm-project/commit/7c9a89fed8f5d53d61fe3a61a2581a7c28b1b6d2
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2020-06-05 (Fri, 05 Jun 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vec_shift5.ll

  Log Message:
  -----------
  [X86] Teach combineVectorShiftImm to constant fold undef elements to 0 not undef.

Shifts are supposed to always shift in zeros or sign bits regardless of their inputs. It's possible the input value may have been replaced with undef by SimplifyDemandedBits, but the shift in zeros are still demanded.

This issue was reported to me by ispc from 10.0. Unfortunately their failing test does not fail on trunk. Seems to be because the shl is optimized out earlier now and doesn't become VSHLI.

ispc bug https://github.com/ispc/ispc/issues/1771

Differential Revision: https://reviews.llvm.org/D81212