[all-commits] [llvm/llvm-project] e50059: [x86] form reduction intrinsics from vectorizers i...

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  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e50059f6b6b32c134e0f4f81281a774cb460524e
      https://github.com/llvm/llvm-project/commit/e50059f6b6b32c134e0f4f81281a774cb460524e
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2020-06-05 (Fri, 05 Jun 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86TargetTransformInfo.h
    M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
    M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr42674.ll
    M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
    M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
    M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
    M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
    M llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
    M llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
    M llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
    M llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reassociated-loads.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction_loads.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
    M llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll
    M llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll
    M llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
    M llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
    M llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll

  Log Message:
  -----------
  [x86] form reduction intrinsics from vectorizers instead of raw IR

Motivating examples are seen in the PhaseOrdering tests based on:
https://bugs.llvm.org/show_bug.cgi?id=43953#c2 - if we have
intrinsics there, some pass can fold them.

The intrinsics are still named "experimental" at this point, but
if there is no fallout from this patch, that will be a good
indicator that it is safe to finalize them.

Differential Revision: https://reviews.llvm.org/D80867