[all-commits] [llvm/llvm-project] 16acc1: AMDGPU/GlobalISel: Fix trying to use wave32 for gf...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 16acc12e1d6b549755674b63fa9d8cbfe217d316
      https://github.com/llvm/llvm-project/commit/16acc12e1d6b549755674b63fa9d8cbfe217d316
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-06-04 (Thu, 04 Jun 2020)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix trying to use wave32 for gfx9 test


  Commit: fe0d5121fa97cd0bbf6d310a2536cc36b435cf5b
      https://github.com/llvm/llvm-project/commit/fe0d5121fa97cd0bbf6d310a2536cc36b435cf5b
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-06-04 (Thu, 04 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix making LDS FP atomics legal on SI/CI


  Commit: 54a8a8d5095fad1993ac3afaf04eb23f3ae06dcb
      https://github.com/llvm/llvm-project/commit/54a8a8d5095fad1993ac3afaf04eb23f3ae06dcb
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-06-04 (Thu, 04 Jun 2020)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
    M llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
    M llvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir
    M llvm/test/CodeGen/AMDGPU/memory_clause.mir
    M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-gpr-idx-mode.mir
    M llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
    M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
    M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
    M llvm/test/CodeGen/AMDGPU/smrd-fold-offset.mir
    M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
    M llvm/test/CodeGen/AMDGPU/wqm.mir

  Log Message:
  -----------
  AMDGPU: Fix using unencodable instructions in tests

There are a number of MIR tests using instructions on subtargets where
they don't really exist. These are some of the easy cases that don't
require splitting up test functions.


Compare: https://github.com/llvm/llvm-project/compare/bd1c03d7b7c8...54a8a8d5095f