[all-commits] [llvm/llvm-project] 9ce0f7: [AMDGPU] Introduce new sched classes for transcend...

[jayfoad via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9ce0f7eed65d5ab6b8e002b06bc3d2d343c836bb
      https://github.com/llvm/llvm-project/commit/9ce0f7eed65d5ab6b8e002b06bc3d2d343c836bb
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-06-04 (Thu, 04 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SISchedule.td
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td

  Log Message:
  -----------
  [AMDGPU] Introduce new sched classes for transcendental instructions

This is in preparation for scheduling them slightly differently on
gfx10. NFC.

Differential Revision: https://reviews.llvm.org/D81011


  Commit: 590964c8353e580a65c21664286a2d3eefbc361c
      https://github.com/llvm/llvm-project/commit/590964c8353e580a65c21664286a2d3eefbc361c
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-06-04 (Thu, 04 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SISchedule.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/cc-update.ll
    M llvm/test/CodeGen/AMDGPU/idot2.ll
    M llvm/test/CodeGen/AMDGPU/idot4s.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8s.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
    M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll

  Log Message:
  -----------
  [AMDGPU] More accurate gfx10 latencies

Differential Revision: https://reviews.llvm.org/D81012


Compare: https://github.com/llvm/llvm-project/compare/52ed34deebb7...590964c8353e