[all-commits] [llvm/llvm-project] a3ada6: [DAGCombiner] Combine shifts into multiply-high

[Amy Kwan via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a3ada630d8abd00930db1c2822427be2301a489e
      https://github.com/llvm/llvm-project/commit/a3ada630d8abd00930db1c2822427be2301a489e
  Author: Amy Kwan <amy.kwan1 at ibm.com>
  Date:   2020-06-02 (Tue, 02 Jun 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    A llvm/test/CodeGen/PowerPC/combine-to-mulh-shift-amount.ll
    A llvm/test/CodeGen/PowerPC/mul-high.ll

  Log Message:
  -----------
  [DAGCombiner] Combine shifts into multiply-high

This patch implements a target independent DAG combine to produce multiply-high
instructions from shifts. This DAG combine will combine shifts for any type as
long as the MULH on the narrow type is legal.

For now, it is enabled on PowerPC as PowerPC is the only target that has an
implementation of the isMulhCheaperThanMulShift TLI hook introduced in
D78271.

Moreover, this DAG combine focuses on catching the pattern:
(shift (mul (ext <narrow_type>:$a to <wide_type>), (ext <narrow_type>:$b to <wide_type>)), <narrow_width>)
to produce mulhs when we have a sign-extend, and mulhu when we have
a zero-extend.

The patch performs the following checks:
- Operation is a right shift arithmetic (sra) or logical (srl)
- Input to the shift is a multiply
- Both operands to the shift are sext/zext nodes
- The extends into the multiply are both the same
- The narrow type is half the width of the wide type
- The shift amount is the width of the narrow type
- The respective mulh operation is legal

Differential Revision: https://reviews.llvm.org/D78272