[all-commits] [llvm/llvm-project] ec0b66: [CodeGen] Specify meaning of ISD opcodes for scala...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ec0b66c318ea42ec229fd3a9ef4ad92bf81d41cf
      https://github.com/llvm/llvm-project/commit/ec0b66c318ea42ec229fd3a9ef4ad92bf81d41cf
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2020-05-28 (Thu, 28 May 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/ISDOpcodes.h

  Log Message:
  -----------
  [CodeGen] Specify meaning of ISD opcodes for scalable vectors

This patch contains changes to the description of EXTRACT_SUBVECTOR,
INSERT_SUBVECTOR, INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT and
CONCAT_VECTORS to specify their behaviour for scalable vectors.

For EXTRACT_SUBVECTOR it specifies that the IDX is scaled by the
same runtime scaling as the extracted (or inserted) vector. This
definition is the most natural extension to EXTRACT_SUBVECTOR for
scalable vectors, as most use-cases that work on fixed-width types
will have the same meaning for scalable types. For legalization for
example, it is common to split the vector operation to operate on
the LO and HI halfs of a vector.

For a fixed width vector <16 x i8> this would be expressed with:

  v16i8 %res = EXTRACT_SUBVECTOR v32i8 %v, i32 16

For a scalable vector, this would similarly be expressed as:

  nxv16i8 %res = EXTRACT_SUBVECTOR nxv32i8 %V, i32 16

By extending the meaning of IDX for scalable vectors, most existing
optimisations on EXTRACT/INSERT_SUBVECTOR work for scalable vectors
without any changes. This definition also allows extracting a
fixed-width subvector from a scalable vector, which is useful to
e.g. extract the low N lanes of a scalable vector.

This patch is not NFC because it sets the meaning of these nodes
for scalable vectors, which future patches will build upon.

Reviewers: efriedma, ctetreau, rogfer01, craig.topper

Reviewed By: efriedma

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79806