[all-commits] [llvm/llvm-project] 8aa81a: AMDGPU/GlobalISel: Fixed handling of non-standard ...

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8aa81aaebe533d0721f1c00deeb0fc452b0147a5
      https://github.com/llvm/llvm-project/commit/8aa81aaebe533d0721f1c00deeb0fc452b0147a5
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2020-05-27 (Wed, 27 May 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fixed handling of non-standard vectors

We do not have register classes for all possible vector
sizes, so round it up for extract vector element.

Also fixes selection of G_MERGE_VALUES when vectors are
not a power of two.

This has required to refactor getRegSplitParts() in way
that it can handle not just power of two vectors.

Ideally we would like RegSplitParts to be generated by
tablegen.

Differential Revision: https://reviews.llvm.org/D80457