[all-commits] [llvm/llvm-project] 4b4496: AMDGPU: Start adding MODE register uses to instruc...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed May 27 11:47:21 PDT 2020 

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 4b4496312e3380d8c427ef836f2b0a38d145652b
      https://github.com/llvm/llvm-project/commit/4b4496312e3380d8c427ef836f2b0a38d145652b
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-05-27 (Wed, 27 May 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrFormats.td
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
    M llvm/lib/Target/AMDGPU/VOPCInstructions.td
    M llvm/lib/Target/AMDGPU/VOPInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
    M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
    M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
    M llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
    M llvm/test/CodeGen/AMDGPU/dead-lane.mir
    M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
    M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
    M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
    M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
    M llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
    M llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
    M llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
    M llvm/test/CodeGen/AMDGPU/hazard.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir
    M llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
    M llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
    M llvm/test/CodeGen/AMDGPU/merge-m0.mir
    M llvm/test/CodeGen/AMDGPU/mode-register.mir
    M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
    M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
    M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
    M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
    M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
    M llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
    M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
    M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
    M llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
    M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    M llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
    M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
    M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
    M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
    M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
    M llvm/unittests/MI/LiveIntervalTest.cpp

  Log Message:
  -----------
  AMDGPU: Start adding MODE register uses to instructions

This is the groundwork required to implement strictfp. For now, this
should be NFC for regular instructoins (many instructions just gain an
extra use of a reserved register). Regalloc won't rematerialize
instructions with reads of physical registers, but we were suffering
from that anyway with the exec reads.

Should add it for all the related FP uses (possibly with some
extras). I did not add it to either the gpr index mode instructions
(or every single VALU instruction) since it's a ridiculous feature
already modeled as an arbitrary side effect.

Also work towards marking instructions with FP exceptions. This
doesn't actually set the bit yet since this would start to change
codegen. It seems nofpexcept is currently not implied from the regular
IR FP operations. Add it to some MIR tests where I think it might
matter.

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